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SC195
3.5MHz, 500mA Synchronous Step Down DC-DC Regulator
POWER MANAGEMENT Features

Description
The SC195 is a high efficiency, 500mA step down regulator designed to operate with an input voltage range of 2.9V to 5.5 V. The input voltage range makes it ideal for battery operated applications with space limitations. The SC195 also includes fifteen programmable output voltage settings that can be selected using the four control pins, eliminating the need for external feedback resistors. The output voltage can be fixed to a single setting or dynamically switched between different levels. Pulling all four control pins low disables the output. The SC195 operates at a fixed 3.5MHz switching frequency in normal PWM (Pulse-Width Modulation) mode. A variable frequency PSAVE (power-save) mode is used to optimize efficiency at light loads for each output setting. Built-in hysteresis prevents chattering between the two modes. The SC195 provides several protection features to safeguard the device under stressed conditions. These include short circuit protection, over-temperature protection, under-voltage lockout, and soft-start to control in-rush current. These features, coupled with the small 1.5 x 1.5 x 0.6 (mm) package make the SC195 a versatile device ideal for step-down regulation in products needing high efficiency and a small PCB footprint.
Input Voltage -- 2.9V to 5.5V Output Voltage -- 0.8V to 3.3V Output current capability -- 500mA Efficiency up to 94% 15 Programmable output voltages High light-load efficiency via automatic PSAVE mode Fast transient response Temperature range -- -40 to +85C Oscillator frequency -- 3.5MHz 100% duty cycle capability Quiescent current -- 38A typ Shutdown Current -- 0.1A typ Internal soft-start Over-voltage protection Current limit and short circuit protection Over-temperature protection Under-voltage lockout Floating control pin protection MLPQ-UT8 1.5 x 1.5 x 0.6 (mm) package Pb free, halogen free, and RoHS/WEEE compliant
Applications

Smart phones and cellular phones MP3/Personal media players Personal navigation devices Digital cameras Single Li-ion cell or 3 NiMH/NiCd cell devices Devices with 3.3V or 5V internal power rails
Typical Application Circuit
VIN 2.9V to 5.5V
SC195
IN CIN 4.7F CTL3 LX OUT
LX 1.0H
VOUT 0.8V to 3.3V
Control Logic Lines
CTL2 CTL1 CTL0
COUT 10F GND
June 29, 2010
(c) 2010 Semtech Corporation
1
SC195
Pin Configuration
CTL3
Ordering Information
Device
SC195ULTRT(1)(2) SC195EVB
8
Package
MLPQ-UT8 1.5 x 1.5 Evaluation Board
CTL2 CTL1 CTL0
1
7
IN LX GND
TOP VIEW
2 6
Notes: (1) Available in tape and reel only. A reel contains 3,000 devices. (2) Lead-free packaging only. Device is WEEE and RoHS compliant and halogen-free.
3 4
5
OUT
MLPQ-UT8; 1.5 x 1.5, 8 LEAD JA = 116C/W
Table 1 - Output Voltage Settings
CTL3 CTL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 CTL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 CTL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Vout Shutdown 0.80 1.00 1.20 1.40 1.50 1.60 1.80 1.85 1.90 2.00 2.20 2.50 2.80 3.00 3.30
Marking Information
0 0 0 0 0
0J yw
0J = SC195 yw = Date code
0 0 0 1 1 1 1 1 1 1 1
2
SC195
Absolute Maximum Ratings
IN (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0 LX Voltage (V). . . . . . . . . . . . . . . . . . . . . . . . . . . .-1.0 to VIN +0.5 Other Pins (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3 to VIN + 0.3 Output Short Circuit to GND . . . . . . . . . . . . . . . . Continuous ESD Protection Level(1) (kV) . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5
Recommended Operating Conditions
Input Voltage Range (V) . . . . . . . . . . . . . . . . . . . . . +2.9 to +5.5 Operating Temperature Range (C) . . . . . . . . . . -40 to +85
Thermal Information
Thermal Resistance, Junction to Ambient(2) (C/W). . . . 116 Junction Temperature Range (C) . . . . . . . . . . . -40 to +150 Storage Temperature Range (C) . . . . . . . . . . . . -65 to +150
Exceeding the above specifications may result in permanent damage to the device or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not recommended. NOTES: (1) Tested according to JEDEC standard JESD22-A114. (2) Calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer FR4 PCB per JESD51 standards.
Electrical Characteristics
Unless otherwise specified: VIN= 3.6V, CIN= 4.7F, COUT=10F, LX=1H, VOUT=1.8V, TJ(MAX)=125C, TA= -40 to +85 C. Typical values are TA=+25 C
Parameter
Output Voltage Range
Symbol
VOUT VOUT_TOL VLINEREG VLOADREG IOUT ILIMIT IFB_LIM VUVLO IQ ISD ILX RDSON_P RDSON_N
Condition
Min
0.8
Typ
Max
3.3 (1) 2.0
Units
V
Output Voltage Tolerance Line Regulation Load Regulation Output Current Capability Current Limit Threshold Foldback Current Limit
IOUT = 200mA PSAVE mode 2.9 VIN 5.5V, IOUT = 200mA 200mA IOUT 500mA
-2.0 1.5 0.3 -1 500 800
% %/V %/A mA 1300 150 2.9 200 38 0.1 0.1 250 m 350 60 1.0 1.0 mA mA V mV A A A
ILOAD > ILIMIT Rising VIN Hysteresis No switching, IOUT = 0mA VCTL 0-3= 0V Into LX pin IOUT= 100mA IOUT= 100mA
Under-Voltage Lockout
Quiescent Current Shutdown Current LX Leakage Current High Side Switch Resistance(2) Low Side Switch Resistance(3)
3
SC195
Electrical Characteristics (continued)
Parameter
Switching Frequency Soft-Start Thermal Shutdown Thermal Shutdown Hysteresis
Symbol
fSW tSS TOT THYST
Condition
Min
2.8
Typ
3.5 100 160 20
Max
4.2 500
Units
MHz s C C
VOUT = 90% of final value Rising temperature
Logic Inputs - CTL0, CTL1, CTL2, and CTL3
Input High Voltage Input Low Voltage Input High Current Input Low Current Notes (1) Maximum output voltage is limited to VIN if the input is less than 3.3V. (2) Measured from IN to LX. (3) Measured from LX to GND. VIH VIL IIH IIL VCTL 0-3= VIN VCTL 0-3= GND -2.0 -2.0 1.2 0.4 5.0 2.0 V V A A
4
SC195
Typical Characteristics
VIN = 4.0V for VOUT = 3.3V, VIN = 3.6V for all others. CIN = 4.7F, COUT = 10F, LX = 1H, TA = 25C unless otherwise noted.
Efficiency vs. IOUT (TA = -40C)
100 90 80 70 3.3V 2.8V 1.8V
Efficiency vs. VOUT (TA = -40C)
100 95 90
Efficiency (%)
IOUT = 200mA
3.6V 4.2V 5.0V
Efficiency (%)
60 50 40 30 20 10 0 0.1
1V
85 80 75 70 65
1
10 Load Current (mA)
100
1000
0.5
1.0
1.5
2.0 VOUT (V)
2.5
3.0
3.5
Efficiency vs. IOUT (TA = 25C)
100 90 80 70
Efficiency (%)
100 IOUT = 200mA
Efficiency vs. VOUT (TA = 25C)
3.3V 2.8V 1.8V 1V
Efficiency (%)
95 90 85 80 75 70 65
3.6V 4.2V 5.0V
60 50 40 30 20 10 0 0.1
1
10 Load Current (mA)
100
1000
0.5
1.0
1.5
2.0 VOUT (V)
2.5
3.0
3.5
Efficiency vs. IOUT (TA = 85C)
100 90 80 70 3.3V 2.8V 1.8V 1V
Efficiency vs. VOUT (TA = 85C)
100 95 90
Efficiency (%)
IOUT = 200mA
3.6V 4.2V 5.0V
Efficiency (%)
60 50 40 30 20 10 0 0.1
85 80 75 70 65 0.5
1
10 Load Current (mA)
100
1000
1.0
1.5
2.0 VOUT (V)
2.5
3.0
3.5
5
SC195
Typical Characteristics (continued)
VIN = 4.0V for VOUT = 3.3V, VIN = 3.6V for all others. CIN = 4.7F, COUT = 10F, LX = 1H, TA = 25C unless otherwise noted.
Frequency vs. Temperature
4
90 89
Efficiency vs. VIN (VOUT =1.8V)
IOUT = 200mA -40C
3.8
1V
1.8V
3.3V
Efficiency (%)
88 87 86 85 84 83 85C 25C
Frequency (MHz)
3.6 2.8V
3.4
3.2
3 -40
-20
0
20 40 Temperature (C)
60
80
100
82
2.5
3.0
3.5
4.0
VIN (V)
4.5
5.0
5.5
Load Regulation (VOUT = 1.8V)
1.86
1.86
Line Regulation (VOUT =1.8V)
IOUT = 200mA
1.84
1.84
Output Voltage (V)
1.82
VOUT (V)
1.82
1.80
85C 25C
1.80
-40C
25C 85C
-40C 1.78
1.78
1.76
0
100
200
300 400 Load Current (mA)
500
600
1.76
2.5
3.0
3.5
4.0 VIN (V)
4.5
5.0
5.5
6
SC195
Typical Characteristics (continued)
Light Load Switching -- VOUT = 1.0V Light Load Switching -- VOUT = 1.8V
VOUT (50mV/div)
VOUT (50mV/div)
VLX (2V/div)
VLX (2V/div)
ILX (200mA/div) Time (400ns/div)
ILX (200mA/div) Time (400ns/div)
Light Load Switching -- VOUT = 2.8V
VOUT (50mV/div) VLX (2V/div)
Light Load Switching -- VOUT = 3.3V
VOUT (50mV/div) VLX (2V/div)
ILX (200mA/div) Time (400ns/div)
ILX (200mA/div) Time (400ns/div)
Heavy Load Switching -- VOUT = 1.0V
VOUT (50mV/div) VOUT (50mV/div)
Heavy Load Switching -- VOUT = 1.8V
VLX (2.0V/div)
VLX (2V/div)
ILX (200mA/div)
ILX (200mA/div)
Time (200ns/div)
Time (200ns/div)
7
SC195
Typical Characteristics (continued)
Heavy Load Switching -- VOUT = 2.8V
VOUT (50mV/div) VOUT (50mV/div)
Heavy Load Switching -- VOUT = 3.3V
VLX (2V/div)
VLX (2V/div)
ILX (200mA/div)
ILX (200mA/div)
Time (200ns/div)
Time (200ns/div)
Heavy Load Soft-start
ILOAD = 500mA ILOAD = 10mA
Light Load Soft-start
IIN (200mA/div) IIN (200mA/div)
VOUT (1.0V/div)
Vout (1.0V/div)
ILX (500mA/div) Time (40s/div)
ILX (500mA/div) Time (40s/div)
Load Transient Response -- 10 to 80mA
Load Transient Response -- 10 to 500mA
VOUT (50mV/div)
VOUT (100mV/div)
ILX (200mA/div) ILX (500mA/div)
ILOAD (50mA/div)
ILOAD (500mA/div)
Time (20s/div)
Time (20s/div)
8
SC195
Typical Characteristics (continued)
Load Transient Response -- 200 to 500mA
VOUT (100mV/div) VOUT (500mV/div)
VID Transient Response -- PWM
1.2V to 1.8V transition
ILX (500mA/div)
ILX (200mA/div)
ILOAD (500mA/div)
VCTL2 (2.0V/div) Time (20s/div) Time (20s/div)
VID Transient Response -- PSAVE
1.2V to 1.8V transition VOUT (2V/div) VOUT (500mV/div) ILX (200mA/div) ILX (200mA/div)
Shutdown Transient Response
VCTL2 (2.0V/div) Time (20s/div)
VCTL3-0 (2V/div) Time (20s/div)
Line Transient Response -- PWM
3.5V to 4.0V transition on VIN
Line Transient Response -- PSAVE
3.5V to 4.0V transition on VIN
VOUT (100mV/div)
VOUT (100mV/div)
ILX (200mA/div)
ILX (200mA/div)
VIN 500mV/div) Time (20s/div)
VIN (500mV/div) Time (40s/div)
9
SC195
Pin Descriptions
Pin
1 2 3 4 5 6 7 8
Pin Name
CTL2 CTL1 CTL0 OUT GND LX IN CTL3
Pin Function
Control bit 2 -- see Table 1, page 2, for decoding. This pin has a weak pull-down resistor (> 1M) in place at reset that is removed when CTL2 is pulled above the logic high threshold. Control bit 1 -- see Table 1, page 2, for decoding. This pin has a weak pull-down resistor (> 1M) in place at reset that is removed when CTL1 is pulled above the logic high threshold. Control bit 0 -- see Table 1, page 2, for decoding. This pin has a weak pull-down resistor (> 1M) in place at reset that is removed when CTL0 is pulled above the logic high threshold. Output voltage sense pin -- output voltage regulation point (connection node of inductor and output capacitor). Ground reference and power ground for the SC195. Switching output -- connect an inductor between this pin and the load to filter the pulsed output current. Input power supply pin -- connect a bypass capacitor from this pin to GND. Control bit 3 -- see Table 1, page 2, for decoding. This pin has a weak pull-down resistor (> 1M) in place at reset that is removed when CTL3 is pulled above the logic high threshold.
10
SC195
Block Diagram
Plimit Amp
8
Current Amp
IN
OSC & Slope Generator Control Logic
PWM Comp
7
LX
500mV Ref
Error Amp
PSAVE Comp
Nlimit Amp
CTL3 CTL2 CTL1 CTL0 OUT
4 3 2 1 5 Voltage Select
6
GND
11
SC195
Applications Information
General Description
The SC195 is a synchronous step-down Pulse Width Modulated (PWM) DC-DC regulator utilizing a 3.5MHz fixed-frequency voltage mode architecture. The device is designed to operate in fixed-frequency PWM mode and enter power save (PSAVE) mode utilizing pulse frequency modulation under light load conditions to maximize efficiency. The device requires only two capacitors and a single inductor to be implemented in most systems. The switching frequency has been chosen to minimize the size of the inductor and capacitors while maintaining high efficiency. The output voltage is programmable, eliminating the need for external programming resistors. Loop compensation is also internal, eliminating the need for external components to control stability. GND or IN. This option allows dynamic voltage adjustment for systems that reduce the supply voltage when entering sleep states. Note that applying all zeros to the CTL pins when changing the output voltages will temporarily disable the device, so it is important to avoid this combination when dynamically changing levels. Adjustable Output Voltage Selection If an output voltage other than one of the 15 programmable settings is needed, an external resistor divider network can be added to the SC195 to adjust the output voltage setting. This network scales the output based on the resistor ratio and the programmed output setting. The resistor values can be determined using the equation
VOUT VSET RFB1 RFB2 RFB2 ILEAK RFB1
Programmable Output Voltage
The SC195 has 15 fixed output voltage levels which can be individually selected by programming the CTL control pins (CTL3-0 -- see Table 1 on page 2 for settings). The device is disabled whenever all four CTL pins are pulled low and enabled whenever at least one of the CTL pins is pulled high. This configuration eliminates the need for a dedicated enable pin. Each CTL pin is internally pulled down via 1M if VIN is below 1.5V or if the voltage on the control pin is below the input high voltage. This ensures that the output is disabled when power is applied if there are no inputs to the CTL pins. Each weak pull-down is disabled whenever its pin is pulled high and remains disabled until all CTL pins are pulled low. The output voltage can be set using different approaches. If a static output voltage is required, the CTL pins can be tied to either IN or GND to set the desired voltage whenever power is applied at IN. If enable control is required, each CTL pin can be tied to either GND or to a microprocessor I/O line to create the desired control code whenever the control signal is forced high. This approach is equivalent to using the CTL pins collectively as a single enable pin. A third option is to connect each of the four CTL pins to individual microprocessor I/O lines. Any of the 15 output voltages can be programmed using this approach. If only two output voltages are needed, the CTL pins can be combined in a way that will reduce the number of I/O lines to 1, 2, or 3, depending on the control code for each desired voltage. Other CTL pins could be hard wired to
where VOUT is the desired output voltage, VSET is the voltage setting selected by the CTL pins, R FB1 is the resistor between the output capacitor and the OUT pin, RFB2 is the resistor between the OUT pin and ground, and ILEAK is the leakage current into the OUT pin during normal operation. The current into the OUT pin is typically 1A, so the last term of the equation can be neglected if the current through RFB2 is much larger than 1A. Selecting a resistor value of 10k or lower will simplify the design. If ILEAK is neglected and RFB2 is fixed, RFB1 can be determined using the equation
RFB1 RFB2 VOUT VSET VSET
Inserting resistance in the feedback loop will adversely affect the system's transient performance if feed-forward capacitance is not included in the circuit. The circuit in Figure 1 illustrates how the resistor divider and feedforward capacitor can be added to the SC195 schematic. The value of feed-forward capacitance needed can be determined using the equation
CFF 4 10
6
RFB1
VSET VOUT 0.5 VOUT VSET VSET
2
0 .5
12
SC195
Applications Information (continued)
SC195
VIN CIN OUT CTL3 CTL2 Enable CTL1 CTL0 GND IN LX LX CFF VOUT
RFB1 RFB2
COUT
increases as VIN decreases to maintain output voltage regulation. As the input voltage approaches the programmed output voltage, the duty cycle approaches 100% (PMOS always on) and the device enters a passthrough mode until the input voltage increases or the load decreases enough to allow PWM switching to resume.
Power Save Mode Operation
When the load current decreases below the PSAVE threshold, PWM switching stops and the device automatically enters PSAVE mode. This threshold varies depending on the input voltage and output voltage setting, optimizing efficiency for all possible load currents in PWM or PSAVE mode. While in PSAVE mode, output voltage regulation is controlled by a series of switching bursts. During a burst, the inductor current is limited to a peak value which controls the on-time of the PMOS switch. After reaching this peak, the PMOS switch is disabled and the inductor current decreases to near 0mA. Switching bursts continue until the output voltage climbs to VOUT +2.5% or until the PSAVE current limit is reached. Switching is then stopped to eliminate switching losses, enhancing overall efficiency. Switching resumes when the output voltage reaches the lower threshold of VOUT and continues until the upper threshold again is reached. Note that the output voltage is regulated hysteretically while in PSAVE mode between VOUT and VOUT + 2.5%. The period and duty cycle while in PSAVE mode are solely determined by VIN and VOUT until PWM mode resumes. This can result in the switching frequency being much lower than the PWM mode frequency. If the output load current increases enough to cause VOUT to decrease below the PSAVE exit threshold (VOUT -2%), the device automatically exits PSAVE and operates in continuous PWM mode. Note that the PSAVE high and low threshold levels are both set at or above VOUT to minimize undershoot when the SC195 exits PSAVE. Figure 2 illustrates the transitions from PWM mode to PSAVE mode and back to PWM mode.
Figure 1 -- Application Circuit with External Resistors To simplify the design, it is recommended to program the output setting to 1.0V, use resistor values smaller than 10k, and include a feed-forward capacitance calculated with the equation above. If the output voltage is set to 1.0V, the previous equation reduces to
CFF 8 10
6
VOUT 0.5 RFB1 VOUT 1
2
Example: An output voltage of 1.3V is desired, but this is not a programmable option. What external component values for Figure 1 are needed? Solution: To keep the circuit simple, set RFB2 to 10k so current into the OUT pin can be neglected and set the CTL3-0 pins to 0010 (1.0V setting). The necessary component values for this situation are
RFB1 RFB 2 VOUT VSET VSET
6
3k
2
CFF
8 10
VOUT 0.5 RFB1 VOUT 1
5.69nF
PWM Operation
Normal PWM operation occurs when the output load current exceeds the PSAVE threshold. In this mode, the PMOS high side switch is activated with the duty cycle required to produce the output voltage programmed by the CTL pins. An internal synchronous NMOS rectifier eliminates the need for an external Schottky diode on the LX pin. The duty cycle (percentage of time PMOS is active)
13
SC195
Applications Information (continued)
Load Demand (IOUT)
VOUT +2.5%
disabled. Switching does not resume until VOUT has fallen below the regulation voltage by 2%.
OFF
VOUT
VOUT -2% BURST
VLX
PWM Mode at Medium/High Load PSAVE Mode at Light Load
PSAVE EXIT PWM Mode at Medium/High Load
Time
Current Limit The SC195 switching stage is protected by a current limit function. If the output load exceeds the PMOS current limit for 32 consecutive switching cycles, the device enters fold-back current limit mode and the output current is limited to approximately 150mA. Under these conditions, the output voltage will be the product of IFB-LIM and the load resistance. The load must fall below IFB-LIM for the device to exit fold-back current limit mode. This function makes the device capable of sustaining an indefinite short circuit on its output under fault conditions. Thermal Shutdown The SC195 has a thermal shutdown feature to protect the device if the junction temperature exceeds 160C. During thermal shutdown, the PMOS and NMOS switches are both disabled, tri-stating the LX output. When the junction temperature drops by the hysteresis value (20C), the device goes through the soft-start process and resumes normal operation. Under-Voltage Lockout Under-Voltage Lockout (UVLO) activates when the supply voltage drops below the UVLO threshold. This prevents the device from entering an ambiguous state in which regulation cannot be maintained. Hysteresis of approximately 200mV is included to prevent chattering near the threshold.
Figure 2 -- Transitions Between PWM and PSAVE Modes
Protection Features
The SC195 provides the following protection features:
* * * * *
Soft-Start Operation Over-Voltage Protection Current Limit Thermal Shutdown Under-Voltage Lockout
Soft-Start The soft-start sequence is activated after a transition from an all zeros CTL code to a non-zero CTL code enables the device. At start-up, the PMOS current limit is stepped through four levels: 25%, 40%, 60%, and 100%. Each step is maintained for 60s following an internal reference start up of 20s, resulting in a total nominal start-up period of 260s. If VOUT reaches 90% of the target within the first 2 steps, the device continues in PSAVE mode at the end of soft-start; otherwise, it goes into PWM mode. Note the VOUT ripple in PSAVE mode can be larger than the ripple in PWM mode. Over-Voltage Protection Over-voltage protection ensures the output voltage does not rise to a level that could damage its load. When VOUT exceeds the regulation voltage by 15%, the PWM drive is
Inductor Selection
The SC195 is designed to operate with a 1H inductor between the LX pin and the OUT pin. Other values may lead to instability, malfunction, or out-of-specification performance. The specified current levels for PSAVE entry, PSAVE exit, and current limit are dependent on the inductor value. The SC195 converter has internal loop compensation. The compensation is designed to work with a specific single-
14
SC195
Applications Information (continued)
pole output filter corner frequency defined by the equation the ripple component of the inductor is a small percentage of the DC load. AC losses in the inductor core and winding do not contribute significantly to the total losses. Magnetic fields associated with the output inductor can interfere with nearby circuitry. This can be minimized by the use of low-noise shielded inductors which use the minimum gap possible to limit the distance that magnetic fields can radiate from the inductor. Shielded inductors, however, typically have a higher DCR and are, therefore, less efficient than a similar sized non-shielded inductor. Final inductor selection depends on various design considerations such as efficiency, EMI, size, and cost. Table 2 lists the manufacturers of recommended inductor options. The inductors with larger packages tend to provide better overall efficiency, while the smaller package inductors provide decent efficiency with reduced footprint or height. The saturation current ratings and DC characteristics are also shown. Table 2 -- Recommended Inductors
Manufacturer Part Number Murata LQM21PN1R0MC0 Murata LQM2HPN1R0MJ0 Murata LQM31PN1R0M00 TaiyoYuden CKP25201R0M-T Toko MDT2012-CR1R0N FDK MIPSZ2012D1R0 FDK MIPSU2520D1R0 FDK MIPSA2520D1R0 TaiyoYuden BRC1608T1R0M L (H) 1.020% 1.020% 1.020% 1.020% 1.030% 1.030% 1.030% 1.330% 1.020% DCR () 0.19 0.09 0.12 0.08 0.08 0.09 0.08 0.09 0.18 Saturation Current (mA) 800 1500 1200 800 1350 1100 1300 1200 850 L at 400mA (H) 0.75 0.95 0.95 0.88 1.00 1.00 0.78 1.20 0.90 Dimensions LxWxH (mm) 2.0x1.25x0.55 2.5x2.0x1.1 3.2x1.6x0.85 2.5x2.0x1.0 2.0x1.25x1.0 2.0x1.25x1.0 2.5x2.0x0.5 2.5x2.0x1.2 1.6x0.8x0.8
where L = 1H and COUT = 10F. When selecting output filter components, the LC product should not vary over a wide range. Selection of smaller inductor and capacitor values will move the corner frequency, potentially impacting system stability. It is also important to consider the change in inductance with DC bias current when choosing an inductor. The inductor saturation current is specified as the current at which the inductance drops a specific percentage from the nominal value (approximately 30%). Except for shortcircuit or other fault conditions, the peak current must always be less than the saturation current specified by the manufacturer. The peak current is the maximum load current plus one half of the inductor ripple current at the maximum input voltage. Load and/or line transients can cause the peak current to exceed this level for short durations. Maintaining the peak current below the inductor saturation specification keeps the inductor ripple current and the output voltage ripple at acceptable levels. Manufacturers often provide graphs of actual inductance and saturation characteristics versus applied inductor current. The saturation characteristics of the inductor can vary significantly with core temperature. Core and ambient temperatures should be considered when examining the core saturation characteristics. When the inductor value has been determined, the DC resistance (DCR) must be examined. Efficiency can be optimized by lowering the inductor's DCR as much as possible. Low DCR in an inductor requires either more surface area for the increased wire diameter or fewer turns to reduce the length of the copper winding. Fewer turns requires an inductor core with a larger cross-sectional area in order to maintain the same saturation characteristics. The inductor size must always be considered when examining the inductor DCR to determine the best compromise between DCR and component area on a PCB. Note that
15
SC195
Applications Information (continued)
COUT Selection The internal voltage loop compensation in the SC195 limits the minimum output capacitor value to 10F. This is due to its influence on the the loop crossover frequency, phase margin, and gain margin. Increasing the output capacitor above this minimum value will reduce the crossover frequency and provide greater phase margin. The output capacitor determines the output voltage ripple and contributes load current during large step load transitions. A capacitor between 10F and 22F will usually be adequate in stabilizing the output during large load transitions. Capacitors with X7R or X5R ceramic dielectric are recommended for their low ESR and superior temperature and voltage characteristics. Y5V capacitors should not be used as their temperature coefficients make them unsuitable for this application. In addition to ensuring stability, the output capacitor serves other important functions. This capacitor determines the output voltage ripple -- as capacitance increases, ripple voltage decreases. It also supplies current during a large load step for a few switching cycles until the control loop responds (typically 3 switching cycles). Once the loop responds, regulation is restored and the desired output is reached. During the period prior to PWM operation resuming, the relationship between output voltage and output capacitance can be approximated using the equation
COUT 3 ILOAD VDROOP f
In this example, using a standard 10F capacitor would be adequate to keep voltage droop less than the desired limit. Note that if the voltage droop limit were decreased from 50mV to 25mV, the output capacitance would need to be increased to at least 12F (twice as much capacitance for half the droop). Capacitance will decrease from the nominal value when a ceramic capacitor is biased with a DC current, so it is important to select a capacitor whose value exceeds the necessary capacitance value at the programmed output voltage. Check the manufacturer's capacitance vs. DC voltage graphs when selecting an output capacitor to ensure the capacitance will be adequate. Table 3 lists the manufacturers of recommended output capacitor options. Table 3 -- Recommended Output Capacitors
Manufacturer Part Nunber Murata GRM188R60J106ME47D Murata GRM21BR60J106K TaiyoYuden JMK107BJ106MA-T TDK C1608X5R0J106MT Value (F) 1020% 1010% 1020% 1020% Type Rated Voltage (VDC) 6.3 6.3 6.3 6.3 Dimensions LxWxH (mm) Case Size 1.6x0.8x0.8 0603 2.0x1.25x1.25 0805 1.6x0.8x0.8 0603 1.6x0.8x0.8 0603
X5R X5R X5R X5R
CIN Selection
This equation can be used to approximate the minimum output capacitance needed to ensure voltage does not droop below an acceptable level. For example, a load step from 50mA to 400mA requiring droop less than 50mV would require the minimum output capacitance to be
COUT 3 0 .4 0.05 4 10 6 6. 0 F
The SC195 input source current will appear as a DC supply current with a triangular ripple imposed on it. To prevent large input voltage ripple, a low ESR ceramic capacitor is required. A minimum value of 4.7F should be used. It is important to consider the DC voltage coefficient characteristics when determining the actual required value. For example, a 10F, 6.3V, X5R ceramic capacitor with 5V DC applied may exhibit a capacitance as low as 4.5F. The value of required input capacitance is estimated by determining the acceptable input ripple voltage and calculating the minimum value required for CIN using the equation
VOUT VOUT 1 VIN VIN V IOUT ESR f
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CIN
SC195
Applications Information (continued)
The input voltage ripple is at maximum level when the input voltage is twice the output voltage (50% duty cycle scenario). The input capacitor provides a low impedance loop for the edges of pulsed current drawn by the PMOS switch. Low ESR/ESL X5R ceramic capacitors are recommended for this function. To minimize stray inductance, the capacitor should be placed as closely as possible to the IN and GND pins of the SC195. Table 4 lists the recommended input capacitor options from different manufacturers. Table 4 -- Recommended Input Capacitors
Manufacturer Part Nunber Murata GRM188R60J475K Murata GRM188R60J106K TaiyoYuden JMK107BJ475KA TDK C1608X5R0J475KT Value (F) 4.710% 1010% 4.710% 4.710% Type Rated Voltage (VDC) 6.3 6.3 6.3 6.3 Dimensions LxWxH (mm) Case Size 1.6x0.8x0.8 0603 1.6x0.8x0.8 0603 1.6x0.8x0.8 0603 1.6x0.8x0.8 0603
CTL3 CTL2 CTL1 CTL0
2. Keep the LX pin traces as short as possible to minimize pickup of high frequency switching edges to other parts of the circuit. COUT and LX should be connected as close as possible between the LX and GND pins, with a direct return to the GND. 3. Use a ground plane referenced to the GND pin. Use several vias to connect to the component side ground to further reduce noise and interference on sensitive circuit nodes. 4. Route the output voltage feedback/sense path away from the inductor and LX node to minimize noise and magnetic interference. 5. Minimize the resistance from the OUT and GND pins to the load. This will reduce errors in DC regulation due to voltage drops in the traces.
4.8mm
X5R X5R X5R X5R
CIN LX
3mm
PCB Layout Considerations
The layout diagram in Figure 3 shows a recommended PCB top-layer for the SC195 and supporting components. Specified layout rules must be followed since the layout is critical for achieving the performance specified in the Electrical Characteristics table. Poor layout can degrade the performance of the DC-DC converter and can contribute to EMI problems, ground bounce, and resistive voltage losses. Poor regulation and instability can result. The following guidelines are recommended for designing a PCB layout: 1. CIN should be placed as close to the IN and GND pins as possible. This capacitor provides a low impedance loop for the pulsed currents present at the buck converter's input. Use short wide traces to minimize trace impedance. This will also minimize EMI and input voltage ripple by localizing the high frequency current pulses.
SC195 COUT
Figure 3 -- Recommended PCB Layout
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SC195
Outline Drawing -- MLPQ-UT8
A
D
B
DIMENSIONS INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX
A A1 A2 b D E e L N aaa bbb .024 .002 (.006) .006 .008 .010 .059 BSC .059 BSC .016 BSC 0.12 .014 0.16 8 .004 .004 .020 .000 0.60 0.05 (0.1524) 0.15 0.20 0.25 1.50 BSC 1.50 BSC 0.40 BSC 0.30 0.35 0.40 8 0.10 0.10 0.50 0.00
PIN 1 INDICATOR (LASER MARK)
E
A2 A aaa C A1 C LxN SEATING PLANE
2 0.20 0.25 0.17 1 N
e
bxN bbb CAB
NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
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SC195
Land Pattern -- MLPQ-UT8
Z G
DIM
C G P R X Y Z
DIMENSIONS INCHES MILLIMETERS
(.057) .028 .016 .004 .008 .030 .087 (1.45) 0.70 0.40 0.10 0.20 0.75 2.20
2X (C)
P
(G) (Z)
X R Y
NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET.
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SC195
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